SN7497N - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN7497N
Manufacturer

TI
ChipWorker Part#

CW31177107
Category

Logic Control, Logic Gate IC
Package

PDIP-16
Description

Multiplier 0°C to 70℃ 16Pin PDIP Tube
Documentation

Datasheet

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SN7497N Specifications

Attribute	Attribute Value

Part Number	SN7497N
Manufacturer	TI
ChipWorker Part#	CW31177107
Category	Logic Control, Logic Gate IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	16 Pin
Case/Package	PDIP-16
Supply Voltage (DC)	4.75V ~ 5.25V
Clock Speed	32 MHz
Number of Bits	6 Bit
Voltage Nodes	5.00 V
Number of Inputs	6 Input
Operating Temperature (Max)	70 ℃
Operating Temperature (Min)	0 ℃
Supply Voltage	4.75V ~ 5.25V
Supply Voltage (Max)	5.25 V
Supply Voltage (Min)	4.75 V
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Size-Length	19.3 mm
Size-Width	6.35 mm
Size-Height	4.57 mm
Operating Temperature	0℃ ~ 70℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN7497N is a 6-bit synchronous Binary-rate Multiplier utilizes series 54/74 TTL circuitry to achieve 32MHz typical maximum operating frequencies. These six-bit serial binary counters feature buffered clock, clear and enable inputs to control the operation of the counter and a strobe input to enable or inhibit the rate input/decoding AND-OR-INVERT gates. The outputs have additional gating for cascading and transferring unity-count rates. The counter is enabled when the clear, strobe and enable inputs are low. With the counter enabled, the output frequency is equal to the input frequency multiplied by the rate input M and divided by 64 i.e. The unity/cascade input, when connected to the clock input, may be utilized to pass the clock frequency (inverted) to the Y output when the rate input/decoding gates are inhibited by the strobe. The unity/cascade input may also be used as a control for the Y output.
Perform fixed-rate or variable-rate frequency division

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