SN74AC373N - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74AC373N
Manufacturer

TI
ChipWorker Part#

CW21688864
Category

Latche IC
Package

PDIP-20
Description

TEXAS INSTRUMENTS SN74AC373N Latch, AC Family, 74AC373, D Type Transparent, Tri State, 10.5ns, 24mA, DIP
Documentation

Datasheet

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SN74AC373N Specifications

Attribute	Attribute Value

Part Number	SN74AC373N
Manufacturer	TI
ChipWorker Part#	CW21688864
Category	Latche IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	20 Pin
Case/Package	PDIP-20
Supply Voltage (DC)	2.00V ~ 6.00V
Number of Outputs	8 Output
Output Current	24 mA
Number of Circuits	8 Circuit
Number of Channels	8 Channel
Number of Positions	20 Position
Number of Bits	8 Bit
Propagation Delay Max (tpd)	9.50 ns
Voltage Nodes	5.00 V, 3.30 V
Output Current Drive	-1.00 mA
Number of Inputs	8 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2V ~ 6V
Supply Voltage (Max)	6 V
Supply Voltage (Min)	2 V
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Size-Length	24.33 mm
Size-Width	6.35 mm
Size-Height	4.57 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN74AC373N is an octal Transparent D Latch with 3-state outputs. It is designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers and working registers. The eight latches are D-type transparent latches. When the LE input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered OE\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines in bus-organized systems without need for interface or pull-up components.
Full parallel access for loading
Maximum tpd of 9.5ns at 5V
3-state Noninverting outputs drive bus lines directly

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