SN74AHC123APWR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74AHC123APWR
Manufacturer

TI
ChipWorker Part#

CW12818193
Category

Flip Flop IC
Package

TSSOP-16
Description

TEXAS INSTRUMENTS SN74AHC123APWR Monostable Multivibrator, 74AHC123, 7.3ns, 8mA, 2V to 5.5V, TSSOP-16
Documentation

Datasheet

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SN74AHC123APWR Specifications

Attribute	Attribute Value

Part Number	SN74AHC123APWR
Manufacturer	TI
ChipWorker Part#	CW12818193
Category	Flip Flop IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	TSSOP-16
Digital Logic Level	CMOS
Supply Voltage (DC)	2.00V ~ 5.50V
Output Current	8 mA
Number of Circuits	2 Circuit
Number of Positions	16 Position
Number of Bits	2 Bit
Voltage Nodes	3.30 V, 5.00 V
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	2 V
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Size-Length	5 mm
Size-Width	4.4 mm
Size-Height	1.15 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN74AHC123APWR is a dual retriggerable Monostable Multivibrator designed for 2 to 5.5V VCC operation. This edge-triggered multivibrator features output pulse-duration control by three methods. In the first method, the A\ input is low and the B input goes high. In the second method, the B input is high and the A\ input goes low. In the third method, the A\ input is low, the B input is high and the clear (CLR\\) input goes high. The output pulse duration is programmed by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR\ low. Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse.
Edge triggered from active-high or active-low gated logic inputs
Retriggerable for very long output pulses
Overriding clear terminates output pulse
Glitch-free power-up reset on outputs
Latch-up performance exceeds 100mA per JESD 78, Class II
Green product and no Sb/Br

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