SN74AHC138PWR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74AHC138PWR
Manufacturer

TI
ChipWorker Part#

CW3302904
Category

Logic Controller, Logic IC
Package

TSSOP-16
Description

3-Line To 8-Line Decoder / Demultiplexer 16-TSSOP -40℃ to 85℃
Documentation

Datasheet

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SN74AHC138PWR Specifications

Attribute	Attribute Value

Part Number	SN74AHC138PWR
Manufacturer	TI
ChipWorker Part#	CW3302904
Category	Logic Controller, Logic IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	TSSOP-16
Supply Voltage (DC)	2.00V ~ 5.50V
Number of Outputs	8 Output
Number of Circuits	1 Circuit
Number of Positions	16 Position
Number of Bits	8 Bit
Voltage Nodes	5.00 V, 3.30 V
Bandwidth	110 MHz
Output Current Drive	-1.00 mA
Number of Inputs	3 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	2 V
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Size-Length	5 mm
Size-Width	4.4 mm
Size-Height	1.15 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2018/06/27
ECCN Code	EAR99

Product Description

The SN74AHC138PWR is a 3-to-8 Decoder/Demultiplexer designed for high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.
Designed specifically for high-speed memory decoders and data-transmission systems
Incorporate three enable inputs to simplify cascading and/or data reception
Latch-up performance exceeds 250mA per JESD 17
Green product and no Sb/Br

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