SN74ALS138AN - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74ALS138AN
Manufacturer

TI
ChipWorker Part#

CW6999993
Category

Logic Controller, Logic IC
Package

PDIP-16
Description

TEXAS INSTRUMENTS SN74ALS138AN Decoder / Demultiplexer, ALS Family, 1 Gate, 3Input, 8 Output, 8mA, 4.5V to 5.5V, DIP-16
Documentation

Datasheet

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SN74ALS138AN Specifications

Attribute	Attribute Value

Part Number	SN74ALS138AN
Manufacturer	TI
ChipWorker Part#	CW6999993
Category	Logic Controller, Logic IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	16 Pin
Case/Package	PDIP-16
Supply Voltage (DC)	4.50V ~ 5.50V
Number of Outputs	8 Output
Number of Circuits	1 Circuit
Number of Positions	16 Position
Number of Bits	8 Bit
Voltage Nodes	5.00 V
Number of Gates	1 Gate
Bandwidth	75.0 MHz
Output Current Drive	-50.0 µA
Number of Inputs	3 Input
Operating Temperature (Max)	70 ℃
Operating Temperature (Min)	0 ℃
Supply Voltage	4.5V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	4.5 V
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Size-Length	19.3 mm
Size-Width	6.35 mm
Size-Height	4.57 mm
Operating Temperature	0℃ ~ 70℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN74ALS138AN is a 3-to-8 Decoder/Demultiplexer designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance systems, these devices can be used to minimize the effects of system decoding. When employed with high-speed memories with a fast enable circuit, the delay times of the decoder and the enable time of the memory are usually less than the typical access time of the memory. The effective system delay introduced by the Schottky-clamped system decoder is negligible. The conditions at the binary-select inputs and the three enable (G1, G2A\ and G2B\\) inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.
Designed specifically for high-speed memory decoders and data transmission systems
Incorporate three enable inputs to simplify cascading and/or data reception

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