SN74AUP1G08DRLR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74AUP1G08DRLR
Manufacturer

TI
ChipWorker Part#

CW5369700
Category

Logic Control, Logic Gate IC
RoHS

Lead free / RoHS Compliant
Description

AND Gate 1Element 2IN CMOS 5Pin SOT T/R
Documentation

Datasheet

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SN74AUP1G08DRLR Specifications

Attribute	Attribute Value

Part Number	SN74AUP1G08DRLR
Manufacturer	TI
ChipWorker Part#	CW5369700
Category	Logic Control, Logic Gate IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	5 Pin
Case/Package	SOT-553-5
Supply Voltage (DC)	800mV ~ 3.60V
Number of Outputs	1 Output
Output Current	4.00 mA
Number of Circuits	1 Circuit
Number of Positions	5 Position
Number of Bits	1 Bit
Propagation Delay Max (tpd)	4.30 ns
Voltage Nodes	3.30 V, 2.50 V
Number of Gates	1 Gate
Output Current Drive	-1.00 mA
Number of Inputs	2 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	0.8V ~ 3.6V
Supply Voltage (Max)	3.6 V
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Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance Edition	2015/06/15

Product Description

DESCRIPTION/ORDERING INFORMATION
The AUP family is TI"s premier solution to the industry"s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC rangeof 0.8 V to 3.6 V, resulting in increased battery life.
FEATURES
• Available in the Texas Instruments NanoStar™ Package
• Low Static-Power Consumption: ICC = 0.9 mA Max
• Low Dynamic-Power Consumption: Cpd = 4.3 pF Typ at 3.3 V
• Low Input Capacitance: Ci = 1.5 pF Typ
• Low Noise: Overshoot and Undershoot <10% of VCC
• Ioff Supports Partial-Power-Down Mode Operation
• Schmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the Input (Vhys = 250 mV Typ at 3.3 V)
• Wide Operating VCC Range of 0.8 V to 3.6 V
• Optimized for 3.3-V Operation
• 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
• tpd = 4.3 ns Max at 3.3 V
• Suitable for Point-to-Point Applications
• Latch-Up Performance Exceeds 100 mA PerJESD 78, Class II
• ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model(A114-B, Class II)
– 1000-V Charged-Device Model (C101)

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