SN74AUP1G17DRLR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74AUP1G17DRLR
Manufacturer

TI
ChipWorker Part#

CW47075490
Category

Logic Control, Logic Gate IC
Package

SOT-553-5
Description

Schmitt Trigger Buffer 1CH Non-Inverting CMOS 5Pin SOT T/R
Documentation

Datasheet

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SN74AUP1G17DRLR Specifications

Attribute	Attribute Value

Part Number	SN74AUP1G17DRLR
Manufacturer	TI
ChipWorker Part#	CW47075490
Category	Logic Control, Logic Gate IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	5 Pin
Case/Package	SOT-553-5
Supply Voltage (DC)	3.30 V, 3.60 V (max)
Number of Positions	5 Position
Number of Bits	1 Bit
Propagation Delay Max (tpd)	5.10 ns, 5.70 ns, 6.20 ns, 7.70 ns
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	0.8V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	0.8 V
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Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
ECCN Code	EAR99

Product Description

DESCRIPTION/ORDERING INFORMATION
The AUP family is TI"s premier solution to the industry"s low-power needs in battery-powered portable
applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life. This product also maintains excellent signal integrity (see Figure 1 and Figure 2).
FEATURES
• Available in the Texas Instruments NanoStar™ Package
• Low Static-Power Consumption (ICC = 0.9 mA Max)
• Low Dynamic-Power Consumption (Cpd = 4.4 pF Typ at 3.3 V)
• Low Input Capacitance (Ci = 1.5 pF Typ)
• Low Noise – Overshoot and Undershoot <10% of VCC
• Ioff Supports Partial-Power-Down Mode Operation
• Includes Schmitt-Trigger Inputs
• Wide Operating VCC Range of 0.8 V to 3.6 V
• Optimized for 3.3-V Operation
• 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
• tpd = 5.1 ns Max at 3.3 V
• Suitable for Point-to-Point Applications
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model (A114-B, Class II)
– 1000-V Charged-Device Model (C101)

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- Vacuum packed
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