SN74AVC2T45DCTR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74AVC2T45DCTR
Manufacturer

TI
ChipWorker Part#

CW2410793
Category

Logic Controller, Logic IC
Package

SSOP-8
Description

TEXAS INSTRUMENTS SN74AVC2T45DCTR Transceiver, 74AVC2T245, 1.2V to 3.6V, SSOP-8
Documentation

Datasheet

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SN74AVC2T45DCTR Specifications

Attribute	Attribute Value

Part Number	SN74AVC2T45DCTR
Manufacturer	TI
ChipWorker Part#	CW2410793
Category	Logic Controller, Logic IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	8 Pin
Case/Package	SSOP-8
Supply Voltage (DC)	1.20V ~ 3.60V
Number of Circuits	1 Circuit
Number of Channels	2 Channel
Number of Positions	8 Position
Number of Bits	2 Bit
Propagation Delay Max (tpd)	2.40 ns
Data Rate	500 Mbps
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Number of Output Channels	1 Channel
Supply Voltage	1.2V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	1.2 V
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Size-Length	3.15 mm
Size-Width	1.2 mm
Size-Height	2.9 mm
Operating Temperature	-40℃ ~ 85℃ (TA)
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN74AVC2T45DCTR is a dual-bit dual-supply Bus Transceiver with configurable voltage translation and 3-state outputs. This 2-bit non-inverting bus transceiver uses two separate configurable power-supply rails. The A ports are designed to track VCCA and accepts any supply voltage from 1.2 to 3.6V. The B port is designed to track VCCB and accepts any supply voltage from 1.2 to 3.6V. The SN74AVC2T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR pin) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic high or low level applied to prevent excess leakage current on the internal CMOS structure.
2-rail design
I/Os are 4.6V tolerant
Partial-power-down mode operation
Latch-up performance exceeds 100mA per JESD 78, class II
ESD protection exceeds JESD 22
Device has limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

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