SN74AVC2T45DCUR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74AVC2T45DCUR
Manufacturer

TI
ChipWorker Part#

CW6870533
Category

Logic Controller, Logic IC
Package

VSSOP-8
Description

Dual-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation and 3-State Outputs 8-VSSOP -40℃ to 85℃
Documentation

Datasheet

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SN74AVC2T45DCUR Specifications

Attribute	Attribute Value

Part Number	SN74AVC2T45DCUR
Manufacturer	TI
ChipWorker Part#	CW6870533
Category	Logic Controller, Logic IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	8 Pin
Case/Package	VSSOP-8
Supply Voltage (DC)	1.20V ~ 3.60V
Number of Circuits	1 Circuit
Number of Channels	2 Channel
Number of Positions	8 Position
Number of Bits	2 Bit
Propagation Delay Max (tpd)	2.40 ns
Data Rate	500 Mbps
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Number of Output Channels	1 Channel
Supply Voltage	1.2V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	1.2 V
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Size-Length	2.3 mm
Size-Width	2 mm
Size-Height	0.85 mm
Operating Temperature	-40℃ ~ 85℃ (TA)
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN74AVC2T45DCUR is a dual-bit dual supply Bus Transceiver with configurable voltage translation and 3-state outputs. This 2-bit non-inverting bus transceiver uses two separate configurable power-supply rails. The A ports are designed to track VCCA and accepts any supply voltage from 1.2 to 3.6V. The B ports are designed to track VCCB and accept any supply voltage from 1.2 to 3.6V. This allows for universal low-voltage bidirectional translation and level-shifting between any of the 1.2/1.5/1.8/2.5/3.3V voltage nodes. The logic levels of the direction-control input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess leakage current on the internal CMOS structure.
Designed for asynchronous communication between two data buses
VCC Isolation
Partial-power-down mode operation
Latch-up performance exceeds 100mA per JESD 78, class II
ESD protection exceeds JESD 22
Green product and no Sb/Br

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