SN74AVC4T774PWR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74AVC4T774PWR
Manufacturer

TI
ChipWorker Part#

CW246490
Category

Logic Controller, Logic IC
Package

TSSOP-16
Description

Transceiver, 1.2V to 3.6V, TSSOP-16
Documentation

Datasheet

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SN74AVC4T774PWR Specifications

Attribute	Attribute Value

Part Number	SN74AVC4T774PWR
Manufacturer	TI
ChipWorker Part#	CW246490
Category	Logic Controller, Logic IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	TSSOP-16
Supply Voltage (DC)	1.20V ~ 3.60V
Number of Outputs	2 Output
Output Current	12 mA
Number of Circuits	1 Circuit
Number of Channels	4 Channel
Number of Positions	16 Position
Number of Bits	4 Bit
Propagation Delay Max (tpd)	2.40 ns
Data Rate	380 Mbps
Number of Inputs	4 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Number of Output Channels	1 Channel
Supply Voltage	1.2V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	1.2 V
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Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN74AVC4T774PW is a 4-bit Non-inverting Bus Transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 to 3.6V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2 to 3.6V. The SN74AVC4T774PW is optimized to operate with VCCA/VCCB set at 1.4 to 3.6V. It is operational with VCCA/VCCB as low as 1.2V. This allows for universal low-voltage bi-directional translation between any of the 1.2, 1.5, 1.8, 2.5 and 3.3V voltage nodes. The SN74AVC4T774PW is designed for asynchronous communication between data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports in the high-impedance mode. The device transmits data from the A bus to the B bus when the B outputs are activated and from the B bus to the A bus when the A outputs are activated.
Each channel has an independent DIR control input
Control inputs VIH/VIL levels are referenced to VCCA voltage
Fully configurable dual-rail design allows each port to operate over full 1.2 to 3.6V power supply
I/Os are 4.6V Tolerant
Ioff supports partial power-down-mode operation
380, 200, 150 and 100Mbps Typical data rates
Latch-up performance exceeds 100mA per JESD 78, class II
Green product and no Sb/Br
Device has limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

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