SN74AVC8T245DGVR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74AVC8T245DGVR
Manufacturer

TI
ChipWorker Part#

CW14086837
Category

Logic Controller, Logic IC
Package

TVSOP-24
Description

Transceiver, 74AVC8T245, 1.2V to 3.6V, TVSOP-24
Documentation

Datasheet

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SN74AVC8T245DGVR Specifications

Attribute	Attribute Value

Part Number	SN74AVC8T245DGVR
Manufacturer	TI
ChipWorker Part#	CW14086837
Category	Logic Controller, Logic IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	24 Pin
Case/Package	TVSOP-24
Supply Voltage (DC)	1.20V ~ 3.60V
Number of Circuits	1 Circuit
Number of Channels	8 Channel
Number of Positions	24 Position
Number of Bits	8 Bit
Propagation Delay Max (tpd)	2.50 ns
Data Rate	320 Mbps
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Number of Output Channels	8 Channel
Supply Voltage	1.2V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	1.2 V
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Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
ECCN Code	EAR99

Product Description

The SN74AVC8T245DGVR is a 8-bit dual-supply Bus Transceiver with configurable voltage-level shifting and 3-state outputs. The bus transceiver uses two separate configurable power-supply rails. It is optimized to operate with VCCA/VCCB set at 1.4 to 3.6V. The device is operational with VCCA/VCCB as low as 1.2V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 to 3.6V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2 to 3.6V. This allows for universal low-voltage bidirectional translation between any of the 1.2/1.5/1.8/2.5/3.3V voltage nodes. It is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the outputs so the buses are effectively isolated. It is designed so the control pins (DIR and OE) are supplied by VCCA.
Control inputs VIH/VIL levels are referenced to VCCA voltage
VCC Isolation - If either VCC input Is at GND, I/O ports are in high-impedance state
IOFF Supports partial power-down mode operation
Fully configurable dual-rail design allows each port to operate over full 1.4 to 3.6V power-supply
I/Os are 4.6V tolerant
Latch-up performance exceeds 100mA per JESD 78, class II
Green product and no Sb/Br

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