SN74HC109N - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74HC109N
Manufacturer

TI
ChipWorker Part#

CW2657233
Category

Flip Flop IC
Package

DIP-16
Description

Flip Flop JK# -Type Pos-Edge 2Element 16Pin PDIP Tube
Documentation

Datasheet

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SN74HC109N Specifications

Attribute	Attribute Value

Part Number	SN74HC109N
Manufacturer	TI
ChipWorker Part#	CW2657233
Category	Flip Flop IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	16 Pin
Case/Package	DIP-16
Frequency	29 MHz
Supply Voltage (DC)	2.00V ~ 6.00V
Number of Outputs	1 Output
Output Current	5.2 mA
Number of Circuits	2 Circuit
Number of Channels	2 Channel
Number of Positions	16 Position
Clock Speed	60 MHz
Number of Bits	2 Bit
Propagation Delay Max (tpd)	37.0 ns
Polarity	Non-Inverting, Inverting
Voltage Nodes	6.00 V, 5.00 V, 2.00 V
Input Capacitance	3 pF
Output Current Drive	-1.00 mA
Number of Inputs	2 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2V ~ 6V
Supply Voltage (Max)	6 V
Supply Voltage (Min)	2 V
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Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2014/12/17

Product Description

The SN74HC109N is a dual positive-edge-triggered J-K Flip-flop with clear and preset. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR are inactive (high), data at the J and K\ inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the J and K\ inputs can be changed without affecting the levels at the outputs. It can perform as toggle flip-flop by grounding K\ and tying J high. It can perform as D-type flip-flops if J and K\ are tied together.
High-current outputs drive up to 10 LSTTL loads
40µA Maximum low power consumption
12ns Typical tpd
±4mA Output drive at 5V
1µA Maximum low input current

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