SN74HC138N - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74HC138N
Manufacturer

TI
ChipWorker Part#

CW118073
Category

Logic Controller, Logic IC
Package

PDIP-16
Description

Decoder / Demultiplexer, HC Family, 8 Output, 5.2mA, 2V to 6V, DIP-16
Documentation

Datasheet

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SN74HC138N Specifications

Attribute	Attribute Value

Part Number	SN74HC138N
Manufacturer	TI
ChipWorker Part#	CW118073
Category	Logic Controller, Logic IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	16 Pin
Case/Package	PDIP-16
Supply Voltage (DC)	2.00V ~ 6.00V
Operating Voltage	2V ~ 6V
Number of Outputs	8 Output
Number of Circuits	1 Circuit
Number of Positions	16 Position
Number of Bits	8 Bit
Voltage Nodes	6.00 V, 5.00 V, 2.00 V
Power Dissipation	320 mW
Bandwidth	28.0 MHz
Output Current Drive	-1.00 mA
Output Current (Max)	5.2 mA
Number of Inputs	3 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2V ~ 6V
Supply Voltage (Max)	6 V
Supply Voltage (Min)	2 V
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Size-Length	19.3 mm
Size-Width	6.35 mm
Size-Height	4.57 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
Mil-Spec	Yes
REACH SVHC Compliance Edition	2014/12/17
ECCN Code	EAR99

Product Description

The SN74HC138N is a 3-line to 8-line Decoder/Demultiplexer, designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. The conditions at the binary-select inputs at the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.
Targeted Specifically for High-speed Memory Decoders and Data-transmission Systems
Outputs Can Drive up to 10 LSTTL Loads
Low-power Consumption, 80µA Maximum ICC
15ns Typical Propagation Delay Time
±4mA Output Drive at 5V
Low Input Current of 1µA Maximum
Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception

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