SN74HC139N - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74HC139N
Manufacturer

TI
ChipWorker Part#

CW761800
Category

Logic Controller, Logic IC
Package

PDIP-16
Description

Decoder / Demultiplexer, HC Family, 4 Output, 5.2mA, 2V to 6V, DIP-16
Documentation

Datasheet

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SN74HC139N Specifications

Attribute	Attribute Value

Part Number	SN74HC139N
Manufacturer	TI
ChipWorker Part#	CW761800
Category	Logic Controller, Logic IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	16 Pin
Case/Package	PDIP-16
Supply Voltage (DC)	2.00V ~ 6.00V
Number of Outputs	4 Output
Contacts Type	DP4T
Number of Circuits	2 Circuit
Number of Positions	16 Position
Number of Bits	4 Bit
Voltage Nodes	6.00 V, 5.00 V, 2.00 V
Power Dissipation	320 mW
Bandwidth	28.0 MHz
Output Current Drive	-1.00 mA
Number of Inputs	2 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2V ~ 6V
Supply Voltage (Max)	6 V
Supply Voltage (Min)	2 V
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Size-Length	19.3 mm
Size-Width	6.35 mm
Size-Height	4.57 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2019/01/15
ECCN Code	EAR99

Product Description

The SN74HC139N is a 2-to-4 dual Decoder/Demultiplexer designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay time of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. The active-low enable (G\\) input can be used as a data line in demultiplexing applications. It features fully buffered inputs, each of which represents only one normalized load to its driving circuit.
Targeted specifically for high-speed memory decoders and data-transmission systems
Incorporate two enable inputs to simplify cascading and/or data reception
Outputs can drive up to 10 LSTTL loads
10ns Typical tpd
80µA Maximum low power consumption
±4mA Output drive at 5V
1µA Maximum low input current

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