SN74HC161D - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74HC161D
Manufacturer

TI
ChipWorker Part#

CW2141204
Category

Logic Controller, Logic IC
Package

SOIC-16
Description

TEXAS INSTRUMENTS SN74HC161D Binary Synchronous Counter, HC Family, 44MHz, 2V to 6V, SOIC-16
Documentation

Datasheet

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SN74HC161D Specifications

Attribute	Attribute Value

Part Number	SN74HC161D
Manufacturer	TI
ChipWorker Part#	CW2141204
Category	Logic Controller, Logic IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	SOIC-16
Frequency	44 MHz
Supply Voltage (DC)	2.00V ~ 6.00V
Number of Outputs	4 Output
Number of Circuits	4 Circuit
Number of Positions	16 Position
Clock Speed	44 MHz
Number of Bits	4 Bit
Voltage Nodes	6.00 V, 5.00 V, 2.00 V
Output Current Drive	-1.00 mA
Number of Inputs	4 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2V ~ 6V
Supply Voltage (Max)	6 V
Supply Voltage (Min)	2 V
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Size-Length	9.9 mm
Size-Width	3.91 mm
Size-Height	1.58 mm
Weight	0.0022670548152 kg
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN74HC161D is a 4-bit presettable Synchronous Binary Counter features an internal carry look-ahead for application in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with synchronous (ripple-clock) counters. A buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform. It is fully programmable, that is, it can be preset to any number between 0 and 9 or 15. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.
Outputs can drive up to 10 LSTTL loads
Internal look-ahead for fast counting
Carry output for n-bit cascading
Synchronous counting
Synchronously programmable
80µA Maximum low power consumption
14ns Typical tpd
±4mA Output drive at 5V
1µA Maximum low input current
Green product and no Sb/Br

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