SN74HC165D - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74HC165D
Manufacturer

TI
ChipWorker Part#

CW1499019
Category

Shift Register IC
Package

SOIC-16
Description

IC: digital; 8Bit, asynchronous, serial out, parallel in; SMD; SO16
Documentation

Datasheet

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SN74HC165D Specifications

Attribute	Attribute Value

Part Number	SN74HC165D
Manufacturer	TI
ChipWorker Part#	CW1499019
Category	Shift Register IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	SOIC-16
Digital Logic Level	CMOS
Supply Voltage (DC)	2.00V ~ 6.00V
Number of Outputs	1 Output
Output Current	5.2 mA
Number of Circuits	1 Circuit
Number of Positions	16 Position
Number of Bits	8 Bit
Propagation Delay Max (tpd)	30.0 ns
Voltage Nodes	6.00 V, 5.00 V, 2.00 V
Output Current Drive	-1.00 mA
Output Current (Max)	5.2 mA
Number of Inputs	9 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2V ~ 6V
Supply Voltage (Max)	6 V
Supply Voltage (Min)	2 V
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Size-Length	9.9 mm
Size-Width	3.91 mm
Size-Height	1.58 mm
Weight	0.0022670548152 kg
Operating Temperature	-40℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN74HC165D is a 8-bit Parallel-load Shift Register features a clock-inhibit (CLK INH) function and a complementary serial (QH) output. The 8-bit parallel-load shift register that, when clocked, shift the data toward a serial (QH) output. Parallel-in access to each stage is provided by eight individual direct data (A-H) inputs that are enabled by a low level at the shift/load (SH/LD) input. Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK INH is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high transition of CLK INH also accomplish clocking, CLK INH should be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD is held high. While SH/LD is low, the parallel inputs to the register are enabled independently of the levels of the CLK, CLK INH or serial (SER) inputs.
Outputs can drive up to 10 LSTTL loads
Low power consumption, 80µA maximum ICC
13ns Typical TPD
±4mA Output drive at 5V
Low input current of 1µA (maximum)
Complementary outputs
Direct overriding load (data) inputs
Gated clock inputs
Parallel-to-serial data conversion
Green product and no Sb/Br

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