SN74HCT138N - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74HCT138N
Manufacturer

TI
ChipWorker Part#

CW5008840
Category

Logic Controller, Logic IC
Package

DIP-16
Description

TEXAS INSTRUMENTS SN74HCT138N Decoder / Demultiplexer, HCT Family, 8 Output, 4mA, 4.5V to 5.5V, DIP-16
Documentation

Datasheet

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SN74HCT138N Specifications

Attribute	Attribute Value

Part Number	SN74HCT138N
Manufacturer	TI
ChipWorker Part#	CW5008840
Category	Logic Controller, Logic IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	16 Pin
Case/Package	DIP-16
Supply Voltage (DC)	4.50V ~ 5.50V
Number of Outputs	8 Output
Output Current	-25.0 mA to 25.0 mA
Number of Circuits	1 Circuit
Number of Positions	16 Position
Number of Bits	8 Bit
Voltage Nodes	5.00 V
Bandwidth	28.0 MHz
Output Current Drive	-1.00 mA
Output Current (Max)	4 mA
Number of Inputs	3 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	4.5V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	4.5 V
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Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN74HCT138N is a 3-line to 8-line Decoder/Demultiplexer designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low (G\\) and one active-high (G) enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.
Outputs can drive up to 10 LSTTL loads
Inputs are TTL-voltage compatible
Designed specifically for high-speed memory decoders and data transmission systems
Incorporate three enable inputs to simplify cascading and/or data reception
80µA Maximum low power consumption
±4mA Output drive at 5V
1µA Maximum low input current

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