SN74HCT373DW - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74HCT373DW
Manufacturer

TI
ChipWorker Part#

CW13625967
Category

Latche IC
Package

SOIC-20
Description

Latch Transparent 3-ST 8CH D-Type 20Pin SOIC Tube
Documentation

Datasheet

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SN74HCT373DW Specifications

Attribute	Attribute Value

Part Number	SN74HCT373DW
Manufacturer	TI
ChipWorker Part#	CW13625967
Category	Latche IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	20 Pin
Case/Package	SOIC-20
Digital Logic Level	CMOS
Supply Voltage (DC)	4.50V ~ 5.50V
Number of Outputs	8 Output
Output Current	6 mA
Number of Circuits	8 Circuit
Number of Channels	8 Channel
Number of Positions	20 Position
Number of Bits	8 Bit
Propagation Delay Max (tpd)	40.0 ns
Polarity	Non-Inverting
Voltage Nodes	5.00 V
Output Current Drive	-1.00 mA
Number of Inputs	8 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	4.5V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	4.5 V
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Size-Length	12.8 mm
Size-Width	7.52 mm
Size-Height	2.35 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN74HCT373DW is an octal transparent D Latch with 3-state outputs. It is designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers and working registers. While the LE input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels that were set up at the D inputs. An OE\ input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pull-up components. OE\ does not affect the internal operations of the latches.
High-current 3-state true outputs can drive up to 15 LSTTL loads
Typical tpd = 21ns
Inputs are TTL-voltage compatible
Full parallel access for loading
80µA Maximum low power consumption
±6mA Output drive at 5V
1µA Maximum low input current
Green product and no Sb/Br

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