SN74LS138D - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LS138D
Manufacturer

TI
ChipWorker Part#

CW2195604
Category

Logic Controller, Logic IC
Package

SOIC-16
Description

TEXAS INSTRUMENTS SN74LS138D Decoder / Demultiplexer, LS Family, 3:8, 4.75V to 5.25V, SOIC-16
Documentation

Datasheet

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SN74LS138D Specifications

Attribute	Attribute Value

Part Number	SN74LS138D
Manufacturer	TI
ChipWorker Part#	CW2195604
Category	Logic Controller, Logic IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	SOIC-16
Supply Voltage (DC)	4.75V ~ 5.25V
Number of Outputs	8 Output
Output Current	8 mA
Number of Circuits	1 Circuit
Number of Channels	1 Channel
Number of Positions	16 Position
Number of Bits	8 Bit
Voltage Nodes	5.00 V
Bandwidth	35 MHz
Output Current Drive	-50.0 µA
Output Current (Max)	8 mA
Number of Inputs	3 Input
Operating Temperature (Max)	70 ℃
Operating Temperature (Min)	0 ℃
Supply Voltage	4.75V ~ 5.25V
Supply Voltage (Max)	5.25 V
Supply Voltage (Min)	4.75 V
	expand all
Size-Length	9.9 mm
Size-Width	3.91 mm
Size-Height	1.58 mm
Weight	0.0022670548152 kg
Operating Temperature	0℃ ~ 70℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN74LS138D is a 3-to-8 Decoder/Demultiplexer designed to be used in high-performance memory decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the Schottky-clamped system decoder is negligible. The LS138 decodes one of eight lines dependent on the conditions at the three binary select inputs and the three enable inputs. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter.
Designed specifically for high-speed
Memory decoders
Data transmission systems
3 Enable inputs to simplify cascading and/or data reception
Schottky-clamped for high performance
Green product and no Sb/Br

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