SN74LS166AN - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LS166AN
Manufacturer

TI
ChipWorker Part#

CW17998303
Category

Shift Register IC
RoHS

Lead free / RoHS Compliant
Description

TEXAS INSTRUMENTS SN74LS166AN Shift Register, LS Family, 74LS166, Parallel to Serial, Serial to Serial, 1Element, 8Bit, DIP
Documentation

Datasheet

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SN74LS166AN Specifications

Attribute	Attribute Value

Part Number	SN74LS166AN
Manufacturer	TI
ChipWorker Part#	CW17998303
Category	Shift Register IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	16 Pin
Case/Package	DIP-16
Frequency	35 MHz
Supply Voltage (DC)	4.75V ~ 5.25V
Number of Outputs	1 Output
Number of Circuits	4 Circuit
Number of Positions	16 Position
Number of Bits	8 Bit
Voltage Nodes	5.00 V
Output Current Drive	-50.0 µA
Number of Inputs	9 Input
Operating Temperature (Max)	70 ℃
Operating Temperature (Min)	0 ℃
Supply Voltage	4.75V ~ 5.25V
Supply Voltage (Max)	5.25 V
Supply Voltage (Min)	4.75 V
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Size-Width	6.35 mm
Operating Temperature	0℃ ~ 70℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN74LS166AN is a 8-bit parallel-load serial-out Shift Register compatible with most other TTL logic families. This parallel-in or serial-in, serial-out shift register has a complexity of 77 equivalent gates on a monolithic chip. It features gated clock inputs and an overriding clear input. The parallel-in or serial-in modes are established by the shift/load input. When high, this input enables the serial data input and couples the eight flip-flops for serial shifting with each clock pulse. When low, the parallel (broadside) data inputs are enabled and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. clocking is accomplished on the low-to-high-level edge of the clock pulse through a two-input positive NOR gate permitting one input to be used as a clock-enable or clock-inhibit function. Holding either of the clock inputs high inhibits clocking, holding either low enables the other clock input.
Synchronous load
Direct overriding clear
Parallel to serial conversion

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