SN74LS173AN - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LS173AN
Manufacturer

TI
ChipWorker Part#

CW8124482
Category

Flip Flop IC
Package

DIP-16
Description

TEXAS INSTRUMENTS SN74LS173AN Flip-Flop, Tri State Non Inverted, Positive Edge, 74LS173, D, 17ns, 50MHz, 24mA, DIP
Documentation

Datasheet

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SN74LS173AN Specifications

Attribute	Attribute Value

Part Number	SN74LS173AN
Manufacturer	TI
ChipWorker Part#	CW8124482
Category	Flip Flop IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	16 Pin
Case/Package	DIP-16
Frequency	50 MHz
Supply Voltage (DC)	4.75V ~ 5.25V
Number of Outputs	4 Output
Output Current	24 mA
Number of Channels	4 Channel
Number of Positions	16 Position
Clock Speed	50 MHz
Number of Bits	4 Bit
Propagation Delay Max (tpd)	30.0 ns
Voltage Nodes	5.00 V
Output Current Drive	-108 µA
Input Current (Min)	0.1 mA
Number of Inputs	4 Input
Operating Temperature (Max)	70 ℃
Operating Temperature (Min)	0 ℃
Supply Voltage	4.75V ~ 5.25V
Supply Voltage (Max)	5.25 V
Supply Voltage (Min)	4.75 V
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Size-Length	19.3 mm
Size-Width	6.35 mm
Size-Height	4.57 mm
Operating Temperature	0℃ ~ 70℃
Product Lifecycle Status	Active
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN74LS173AN is a 4-bit D-type Register with 3-state outputs. It features totem-pole 3-state outputs capable of driving highly capacitive or relatively low-impedance loads. The high-impedance third state and increased high-logic-level drive provide these flip-flops with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the output control circuitry is designed so that the average output disable times are shorter than the average output enable times. Gated enable inputs are provided on these devices for controlling the entry of data into the flip-flops. When both data-enable (G1\, G2\\) inputs are low, data at the D inputs are loaded into their respective flip-flops on the next positive transition of the buffered clock input. Gate output-control (M, N) inputs also are provided.
Gated output-control lines for enabling or disabling the outputs
Fully independent clock virtually eliminates restrictions for operating in parallel load
Fully independent clock virtually eliminates restrictions for operating in do nothing (hold)
TTL Input and output

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