SN74LS191N - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LS191N
Manufacturer

TI
ChipWorker Part#

CW7983981
Category

Counter, Counter IC
Package

PDIP-16
Description

TEXAS INSTRUMENTS SN74LS191N Binary Synchronous Up / Down Counter, LS Family, 25MHz, 4.75V to 5.25V, DIP-16
Documentation

Datasheet

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SN74LS191N Specifications

Attribute	Attribute Value

Part Number	SN74LS191N
Manufacturer	TI
ChipWorker Part#	CW7983981
Category	Counter, Counter IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	16 Pin
Case/Package	PDIP-16
Frequency	25 MHz
Digital Logic Level	CMOS
Supply Voltage (DC)	4.75V ~ 5.25V
Number of Outputs	4 Output
Number of Circuits	1 Circuit
Number of Positions	16 Position
Clock Speed	25 MHz
Number of Bits	4 Bit
Voltage Nodes	5.00 V
Output Current Drive	-50.0 µA
Number of Inputs	4 Input
Operating Temperature (Max)	70 ℃
Operating Temperature (Min)	0 ℃
Supply Voltage	4.75V ~ 5.25V
Supply Voltage (Max)	5.25 V
Supply Voltage (Min)	4.75 V
	expand all
Size-Length	19.3 mm
Size-Width	6.35 mm
Size-Height	4.57 mm
Weight	0.015227096868 kg
Operating Temperature	0℃ ~ 70℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN74LS191N is a 4-bit synchronous Up/Down Counter with up/down mode control. It has a complexity of 58 equivalent gates. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous counters. The outputs of the four master-slave flip-flops are triggered on a low-to-high transition of the clock input if the enable input is low. A high at the enable input inhibits counting. Level changes at the enable input should be made only when the clock input is high. The direction of the count is determined by the level of the down/up input. When low, the counter count up and when high, it counts down. A false clock may occur if the down/up input changes while the clock is low.
Counts 8-4-2-1 BCD or binary
Single down/up count control line
Count enable control input
Ripple clock output for cascading
Asynchronously presettable with load control
Parallel outputs
Cascadable for N-bit applications

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