SN74LS373N - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LS373N
Manufacturer

TI
ChipWorker Part#

CW1219300
Category

Latche IC
Package

DIP-20
Description

Latch Transparent 3-ST 8Channel D-Type 20Pin Plastic Dip Tube
Documentation

Datasheet

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SN74LS373N Specifications

Attribute	Attribute Value

Part Number	SN74LS373N
Manufacturer	TI
ChipWorker Part#	CW1219300
Category	Latche IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	20 Pin
Case/Package	DIP-20
Supply Voltage (DC)	4.75V ~ 5.25V
Number of Outputs	8 Output
Output Current	24 mA
Number of Circuits	8 Circuit
Number of Channels	8 Channel
Number of Positions	20 Position
Number of Bits	8 Bit
Propagation Delay Max (tpd)	18.0 ns
Polarity	Non-Inverting
Voltage Nodes	5.00 V
Quiescent Current	24.0 mA
Output Current Drive	-108 µA
Number of Inputs	8 Input
Operating Temperature (Max)	70 ℃
Operating Temperature (Min)	0 ℃
Supply Voltage	4.75V ~ 5.25V
Supply Voltage (Max)	5.25 V
Supply Voltage (Min)	4.75 V
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Size-Length	24.33 mm
Size-Width	6.35 mm
Size-Height	4.57 mm
Operating Temperature	0℃ ~ 70℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
ECCN Code	EAR99

Product Description

The SN74LS373N is an octal D-type Transparent Latch with 3-state outputs. Designed specifically for driving highly capacitive or relatively low-impedance loads. The high-impedance 3-state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull up components. This device is particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers and working registers. The eight latches of the LS373 is transparent D-type latches, meaning that while the enable (C or CLK) input is high, the Q-outputs follow the data (D)-inputs. When C or CLK is taken low, the output is latched at the level of the data that was set up.
3-state Bus-driving outputs
Full parallel access for loading
Buffered control inputs
Clock-enable input has hysteresis to improve noise rejection
PNP inputs reduce DC loading on data lines

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