SN74LS374N - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LS374N
Manufacturer

TI
ChipWorker Part#

CW2102635
Category

Flip Flop IC
Package

DIP-20
Description

TEXAS INSTRUMENTS SN74LS374N Flip-Flop, Tri State Non Inverted, Positive Edge, 74LS374, D, 15ns, 50MHz, 24mA, DIP
Documentation

Datasheet

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SN74LS374N Specifications

Attribute	Attribute Value

Part Number	SN74LS374N
Manufacturer	TI
ChipWorker Part#	CW2102635
Category	Flip Flop IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	20 Pin
Case/Package	DIP-20
Frequency	50 MHz
Supply Voltage (DC)	4.75V ~ 5.25V
Number of Outputs	8 Output
Output Current	24 mA
Number of Circuits	8 Circuit
Number of Channels	8 Channel
Number of Positions	20 Position
Clock Speed	50 MHz
Number of Bits	8 Bit
Propagation Delay Max (tpd)	28.0 ns
Polarity	Non-Inverting
Voltage Nodes	5.00 V
Output Current Drive	-108 µA
Number of Inputs	8 Input
Operating Temperature (Max)	70 ℃
Operating Temperature (Min)	0 ℃
Supply Voltage	4.75V ~ 5.25V
Supply Voltage (Max)	5.25 V
Supply Voltage (Min)	4.75 V
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Size-Length	24.33 mm
Size-Width	6.35 mm
Size-Height	4.57 mm
Weight	0.0191855977428 kg
Operating Temperature	0℃ ~ 70℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN74LS374N is an octal D-type Edge Triggered Flip-Flop with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The high-impedance 3-state and increased high-logic-level drive provide this register with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. This device is particularly attractive for implementing buffer registers and I/O ports, bidirectional bus drivers and working registers. On the positive transition of the clock and the Q outputs are set to the logic states that were set up at the D inputs. Schmitt-trigger buffered inputs at the enable/clock lines of the S374 device simplify system design as AC and DC noise rejection is improved by typically 400mV due to the input hysteresis. A buffered output-control input can be used to place the eight outputs in either a normal logic state or the high-impedance state.
Full parallel access for loading
Buffered control inputs
Clock-enable input has hysteresis to improve noise rejection
PNP Inputs reduce DC loading on data lines
Pb-free product

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