SN74LS85N - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LS85N
Manufacturer

TI
ChipWorker Part#

CW3408908
Category

Logic Control, Logic Gate IC
Package

PDIP-16
Description

Digital Comparator, 74LS85, Magnitude, 4Channels, 4Bit, DIP, 16Pins
Documentation

Datasheet

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SN74LS85N Specifications

Attribute	Attribute Value

Part Number	SN74LS85N
Manufacturer	TI
ChipWorker Part#	CW3408908
Category	Logic Control, Logic Gate IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	16 Pin
Case/Package	PDIP-16
Supply Voltage (DC)	5.00 V, 5.25 V (max)
Supply Current	10.4 mA
Number of Channels	4 Channel
Number of Positions	16 Position
Number of Bits	4 Bit
Voltage Nodes	5.00 V
Operating Temperature (Max)	70 ℃
Operating Temperature (Min)	0 ℃
Supply Voltage	4.75V ~ 5.25V
Supply Voltage (Max)	5.25 V
Supply Voltage (Min)	4.75 V
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Size-Length	19.3 mm
Size-Width	6.35 mm
Size-Height	4.57 mm
Operating Temperature	0℃ ~ 70℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN74LS85N is a 4-bit Magnitude Comparator performs comparison of straight binary and straight BCD (8-4-2-1) codes. Three fully decoded decisions about two 4-bit words (A, B) are made and are externally available at three outputs. This device is fully expandable to any number of bits without external gates. Words of greater length may be compared by connecting comparators in cascade. The A > B, A < B and A = B outputs of a stage handling less-significant bits are connected to the corresponding A > B, A < B and A = B inputs of the next stage handling more-significant bits. The stage handling the least-significant bits must have a high-level voltage applied to the A = B input. The cascading paths of the S85 is implemented with only a two-gate-level delay to reduce overall comparison times for long words. An alternate method of cascading which further reduces the comparison time is shown in the typical application data.

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