SN74LV08APWR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LV08APWR
Manufacturer

TI
ChipWorker Part#

CW6117279
Category

Logic Control, Logic Gate IC
Package

TSSOP-14
Description

AND Gate 4Element 2IN CMOS 14Pin TSSOP T/R
Documentation

Datasheet

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SN74LV08APWR Specifications

Attribute	Attribute Value

Part Number	SN74LV08APWR
Manufacturer	TI
ChipWorker Part#	CW6117279
Category	Logic Control, Logic Gate IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	14 Pin
Case/Package	TSSOP-14
Supply Voltage (DC)	2.00V ~ 5.50V
Number of Outputs	1 Output
Output Current	12.0 mA
Number of Circuits	4 Circuit
Number of Positions	14 Position
Number of Bits	4 Bit
Propagation Delay Max (tpd)	20.0 ns
Voltage Nodes	5.00 V, 3.30 V, 2.50 V
Number of Gates	4 Gate
Output Current Drive	-1.00 mA
Number of Inputs	2 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	2 V
	expand all
Size-Length	5 mm
Size-Width	4.4 mm
Size-Height	1.15 mm
Operating Temperature	-40℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

description/ordering information
These quadruple 2-input positive-AND gates are designed for 2-V to 5.5-V VCC operation. The ’LV08A devices perform the Boolean function Y = A • B or Y = A + B in positive logic.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
• 2-V to 5.5-V VCC Operation
• Max tpd of 7 ns at 5 V
• Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
• Support Mixed-Mode Voltage Operation on All Ports
• Ioff Supports Partial-Power-Down Mode Operation
• Latch-Up Performance Exceeds 250 mA Per JESD 17
• ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)

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