SN74LV123APWR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LV123APWR
Manufacturer

TI
ChipWorker Part#

CW4013993
Category

Flip Flop IC
Package

TSSOP-16
Description

Monostable Multivibrator, 74LV123, 8.3ns, 25mA, 2V to 5.5V, TSSOP-16
Documentation

Datasheet

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SN74LV123APWR Specifications

Attribute	Attribute Value

Part Number	SN74LV123APWR
Manufacturer	TI
ChipWorker Part#	CW4013993
Category	Flip Flop IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	TSSOP-16
Digital Logic Level	TTL
Supply Voltage (DC)	2.00V ~ 5.50V
Output Current	25 mA
Number of Circuits	2 Circuit
Number of Positions	16 Position
Number of Bits	2 Bit
Voltage Nodes	2.50 V, 3.30 V, 5.00 V
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	2 V
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Size-Length	5 mm
Size-Width	4.4 mm
Size-Height	1.15 mm
Operating Temperature	-40℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15

Product Description

The SN74LV123APWR is a dual retriggerable Monostable Multivibrator designed for 2 to 5.5V VCC operation. It features output pulse-duration control by three methods. In the first method, the A input is low and the B input goes high. In the second method, the B input is high and the A\ input goes low. In the third method, the A\ input is low, the B input is high and the clear (CLR/) input goes high. The output pulse duration is programmable by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR\ low.
Support mixed-mode voltage operation on all ports
Schmitt-trigger circuitry on A\, B and CLR\ inputs for slow input transition rates
Edge triggered from active-high or active-low gated logic inputs
Ioff Supports partial-power-down mode operation
Retriggerable for very long output pulses, up to 100% duty cycle
Overriding clear terminates output pulse
Glitch-free power-up reset on outputs
Latch-up performance exceeds 100mA per JESD 78, Class II
Green product and no Sb/Br

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