SN74LV573APW - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LV573APW
Manufacturer

TI
ChipWorker Part#

CW25201666
Category

Latche IC
Package

TSSOP-20
Description

Latch Transparent 3-ST 8CH D-Type 20Pin TSSOP Tube
Documentation

Datasheet

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SN74LV573APW Specifications

Attribute	Attribute Value

Part Number	SN74LV573APW
Manufacturer	TI
ChipWorker Part#	CW25201666
Category	Latche IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	20 Pin
Case/Package	TSSOP-20
Supply Voltage (DC)	2.00V ~ 5.50V
Number of Outputs	8 Output
Output Current	16 mA
Number of Circuits	8 Circuit
Number of Positions	20 Position
Number of Bits	8 Bit
Voltage Nodes	5.00 V, 3.30 V, 2.50 V
Number of Inputs	8 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	2 V
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Size-Length	6.5 mm
Size-Width	4.4 mm
Size-Height	1.15 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN74LV573APW is an octal transparent D-type Latch with 3-state outputs. It is designed for 2 to 5.5V VCC operation. It features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers and working registers. While the LE input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered OE\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pull-up components.
Support mixed-mode voltage operation on all ports
Ioff Supports partial-power-down mode operation
Latch-up performance exceeds 250mA per JESD 17
Green product and no Sb/Br

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