SN74LV8151PW - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LV8151PW
Manufacturer

TI
ChipWorker Part#

CW18645496
Category

Logic Controller, Logic IC
Package

TSSOP-24
Description

Universal Schmitt Trigger Buffer 10CH Inverting/Non-Inverting 3-ST CMOS 24Pin TSSOP Tube
Documentation

Datasheet

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SN74LV8151PW Specifications

Attribute	Attribute Value

Part Number	SN74LV8151PW
Manufacturer	TI
ChipWorker Part#	CW18645496
Category	Logic Controller, Logic IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	24 Pin
Case/Package	TSSOP-24
Supply Voltage (DC)	2.00V ~ 5.50V
Number of Outputs	10 Output
Number of Circuits	1 Circuit
Number of Channels	10 Channel
Number of Positions	24 Position
Number of Bits	10 Bit
Propagation Delay Max (tpd)	17.0 ns
Voltage Nodes	2.50 V, 3.30 V, 5.00 V
Number of Gates	10 Gate
Output Current Drive	-1.00 mA
Number of Inputs	10 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	2 V
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Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN74LV8151PW is a 10-bit universal Schmitt-Trigger Buffer with 3-state outputs designed for 2 to 5.5V VCC operation. The logic control (T/C\\) pin allows the user to configure Y1 to Y8 as non-inverting or inverting outputs. When T/C\ is high, the Y-outputs are non-inverted (true logic ) and when T/C\ is low, the Y-outputs are inverted (complementary logic). When output-enable (OE)\ input is low, the device passes data from Dn to Yn. When OE\ is high, the Y-outputs are in the high-impedance state. The path A to P is a simple Schmitt-trigger buffer and the path B to N is a simple Schmitt-trigger inverter. This device is fully specified for partial-power-down applications using IOFF. The IOFF circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
15ns at 5V Maximum TPD
Schmitt-trigger inputs allow for slow input rise or fall time
Polarity control for Y-outputs selects true or complementary logic
IOFF supports partial-power-down mode operation
Supports mixed-mode voltage operation on all ports
Latch-up performance exceeds 250mA per JESD 17
ESD protection exceeds JESD 22

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