SN74LVC125ADR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LVC125ADR
Manufacturer

TI
ChipWorker Part#

CW2031882
Category

Logic Controller, Logic IC
Package

SOIC-14
Description

Buffer/Line Driver 4CH Non-Inverting 3-ST CMOS 14Pin SOIC T/R
Documentation

Datasheet

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SN74LVC125ADR Specifications

Attribute	Attribute Value

Part Number	SN74LVC125ADR
Manufacturer	TI
ChipWorker Part#	CW2031882
Category	Logic Controller, Logic IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	14 Pin
Case/Package	SOIC-14
Supply Voltage (DC)	1.65V ~ 3.60V
Number of Outputs	4 Output
Number of Circuits	4 Circuit
Number of Channels	4 Channel
Number of Positions	14 Position
Number of Bits	4 Bit
Propagation Delay Max (tpd)	4.80 ns
Voltage Nodes	3.30 V, 2.70 V, 2.50 V, 1.80 V
Power Dissipation	500 mW
Number of Gates	4 Gate
Output Current Drive	-1.00 mA
Number of Inputs	4 Input
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	500 mW
Supply Voltage	1.65V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	1.65 V
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Size-Length	8.65 mm
Size-Width	3.91 mm
Size-Height	1.58 mm
Operating Temperature	-40℃ ~ 125℃ (TA)
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN74LVC125ADR is a Quadruple Bus Buffer Gate, designed for 1.65 to 3.6V VCC operation. The SN74LVC125ADR device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor, the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven from either 3.3 or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3/5V system environment. ESD protection exceeds JESD 22, 2000V human-body model, 200V machine model and 1000V charged-device model.
3-state Outputs
Separate OE for all 4 buffers
Inputs accept voltages to 5.5V
Maximum TPD of 4.8ns at 3.3V
<0.8V at VCC = 3.3V, TA = 25°C Typical VOLP (output ground bounce)
>2V at VCC = 3.3V, TA = 25°C Typical VOHV (output VOH undershoot)
Latch-up performance exceeds 250mA per JESD 17
Green product and no Sb/Br
Device has limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

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