SN74LVC16373ADGGR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LVC16373ADGGR
Manufacturer

TI
ChipWorker Part#

CW1134012
Category

Latche IC
Package

TSSOP-48
Description

Latch Transparent 3-ST 16CH D-Type 48Pin TSSOP T/R
Documentation

Datasheet

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SN74LVC16373ADGGR Specifications

Attribute	Attribute Value

Part Number	SN74LVC16373ADGGR
Manufacturer	TI
ChipWorker Part#	CW1134012
Category	Latche IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	48 Pin
Case/Package	TSSOP-48
Supply Voltage (DC)	1.65V ~ 3.60V
Number of Outputs	16 Output
Output Current	24 mA
Number of Circuits	8 Circuit
Number of Channels	16 Channel
Number of Positions	48 Position
Number of Bits	16 Bit
Propagation Delay Max (tpd)	4.60 ns
Polarity	Non-Inverting
Voltage Nodes	3.30 V, 2.70 V, 2.50 V, 1.80 V
Output Current Drive	-1.00 mA
Number of Inputs	16 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	1.65V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	1.65 V
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Size-Length	12.6 mm
Size-Width	6.2 mm
Size-Height	1.05 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN74LVC16373ADGGR is a 16-bit transparent D Latch with 3-state outputs. It is designed for 1.65 to 3.6V VCC operation. The device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers and working registers. The device can be used as two 8-bit latches or one 16-bit latch. When the LE input high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. A buffered OE\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
Member of the Texas Instruments Widebus™ family
Ioff Supports live-insertion, partial-power-down mode and back-drive protection
Supports mixed-mode signal operation
Latch-up performance exceeds 100mA per JESD, 78 class II
Green product and no Sb/Br

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