SN74LVC1G123DCUR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LVC1G123DCUR
Manufacturer

TI
ChipWorker Part#

CW1202882
Category

Flip Flop IC
Package

VSSOP-8
Description

Monostable Multivibrator, 74LVC1G123, 18.5ns, 50mA, 1.65V to 5.5V, VSSOP-8
Documentation

Datasheet

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SN74LVC1G123DCUR Specifications

Attribute	Attribute Value

Part Number	SN74LVC1G123DCUR
Manufacturer	TI
ChipWorker Part#	CW1202882
Category	Flip Flop IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	8 Pin
Case/Package	VSSOP-8
Supply Voltage (DC)	1.65V (min)
Output Current	50 mA
Number of Positions	8 Position
Number of Bits	1 Bit
Propagation Delay Max (tpd)	8.20 ns
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	1.65V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	1.65 V
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Size-Width	2 mm
Size-Height	0.8 mm
Operating Temperature	-40℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15

Product Description

The SN74LVC1G123DCUR is a single retriggerable Monostable Multivibrator designed for 1.65 to 5.5V VCC operation. It features output pulse-duration control by three methods. In the first method, the A\ input is low and the B input goes high. In the second method, the B input is high and the A input goes low. In the third method, the A\ input is low, the B input is high and the clear (CLR\\) input goes high. The output pulse duration is programmed by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR\ low. Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse.
Supports mixed-mode voltage operation on all ports
Supports down translation to VCC
Schmitt-trigger circuitry on A\ and B inputs for slow input transition rates
Edge triggered from active-high or active-low gated logic inputs
Retriggerable for very long output pulses, up to 100% duty cycle
Overriding clear terminates output pulse
Glitch-free power-up reset on outputs
Ioff Supports live insertion, partial-power-down mode and back-drive protection
Latch-up performance exceeds 100mA per JESD 78, Class II
Green product and no Sb/Br

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