SN74LVC1G14DRLR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LVC1G14DRLR
Manufacturer

TI
ChipWorker Part#

CW13672719
Category

Logic Control, Logic Gate IC
Package

SOT-553
Description

Inverter Schmitt Trigger 1Element CMOS 5Pin SOT T/R
Documentation

Datasheet

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SN74LVC1G14DRLR Specifications

Attribute	Attribute Value

Part Number	SN74LVC1G14DRLR
Manufacturer	TI
ChipWorker Part#	CW13672719
Category	Logic Control, Logic Gate IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	5 Pin
Case/Package	SOT-553
Supply Voltage (DC)	5.00 V
Output Current	32 A
Number of Circuits	1 Circuit
Number of Positions	5 Position
Number of Bits	1 Bit
Propagation Delay Max (tpd)	5.00 ns
Number of Gates	1 Gate
Output Current Drive	-1.00 mA
Number of Inputs	1 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	1.65V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	1.65 V
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Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Cut Tape (CT)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN74LVC1G14DRLR is a single Schmitt-trigger Inverter. The device performs the Boolean function Y = A\\. The device functions as an independent inverter, but because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT-) signals. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
±24mA Output drive at 3.3V
10µA Maximum ICC low power consumption
Inputs accept voltages to 5.5V
Maximum tpd of 4.6ns at 3.3V
Ioff supports partial-power-down mode operation
ESD protection exceeds JESD 22
Latch-up performance exceeds 100mA per JESD 78, Class II

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