SN74LVC1G175DBVT - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LVC1G175DBVT
Manufacturer

TI
ChipWorker Part#

CW4136004
Category

Flip Flop IC
Package

SOT-23-6
Description

Flip-Flop, 74LVC1G175, D, 3.2ns, 175MHz, 32mA, SOT-23
Documentation

Datasheet

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SN74LVC1G175DBVT Specifications

Attribute	Attribute Value

Part Number	SN74LVC1G175DBVT
Manufacturer	TI
ChipWorker Part#	CW4136004
Category	Flip Flop IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	6 Pin
Case/Package	SOT-23-6
Frequency	175 MHz
Supply Voltage (DC)	1.65V (min)
Number of Outputs	1 Output
Output Current	32 mA
Number of Circuits	1 Circuit
Number of Channels	1 Channel
Number of Positions	6 Position
Clock Speed	175 MHz
Number of Bits	1 Bit
Propagation Delay Max (tpd)	3.00 ns, 3.20 ns
Input Capacitance	3 pF
Number of Inputs	1 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	1.65V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	1.65 V
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Size-Length	2.9 mm
Size-Width	1.6 mm
Size-Height	1.15 mm
Operating Temperature	-40℃ ~ 125℃ (TA)
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN74LVC1G175DBVT is a single D-type Flip-flop with asynchronous clear. The SN74LVC1G175 device has an asynchronous clear (CLR) input. When CLR is high, data from the input pin (D) is transferred to the output pin (Q) on the clock"s (CLK) rising edge. When CLR is low, Q is forced into the low state, regardless of the clock edge or data on D.
Supports down translation to VCC
4.3ns at 3.3V Maximum TPD
Low power consumption
IOFF supports live insertion, partial-power-down mode and back-drive protection
Latch-up performance exceeds 100mA per JESD 78
ESD protection exceeds JESD 22
This device has limited built-in ESD protection, leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

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