SN74LVC1G17DRLR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LVC1G17DRLR
Manufacturer

TI
ChipWorker Part#

CW1967593
Category

Logic Control, Logic Gate IC
Package

SOT-553
Description

Schmitt Trigger Buffer, 1Channel, 1.65V to 5.5V, SOT-553-5
Documentation

Datasheet

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SN74LVC1G17DRLR Specifications

Attribute	Attribute Value

Part Number	SN74LVC1G17DRLR
Manufacturer	TI
ChipWorker Part#	CW1967593
Category	Logic Control, Logic Gate IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	5 Pin
Case/Package	SOT-553
Supply Voltage (DC)	1.65V ~ 5.50V
Number of Outputs	1 Output
Number of Channels	1 Channel
Number of Positions	5 Position
Number of Bits	1 Bit
Propagation Delay Max (tpd)	5.00 ns
Number of Gates	1 Gate
Output Current Drive	-1.00 mA
Number of Inputs	1 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	1.65V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	1.65 V
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Size-Length	1.7 mm
Size-Width	1.3 mm
Size-Height	0.55 mm
Operating Temperature	-40℃ ~ 125℃ (TA)
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15

Product Description

The SN74LVC1G17DRLR is a single Schmitt-trigger Buffer is designed for 1.65 to 5.5V VCC operation. It contains one buffer and performs the boolean function Y = A. The CMOS device has high output drive while maintaining low static power dissipation over a broad Vcc operating range. The device functions as an independent buffer, but because of Schmitt action, it will have different input threshold levels for a positive-going (VT+) and negative-going signals. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Ioff Supports live insertion, partial-power-down mode and back-drive protection
Latch-up performance exceeds 100mA per JESD 78, class II
Maximum tpd of 4.6ns at 3.3V
10µA Maximum low power consumption
±24mA Output drive at 3.3V
Green product and no Sb/Br

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