SN74LVC1G3208DBVR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LVC1G3208DBVR
Manufacturer

TI
ChipWorker Part#

CW8111392
Category

Logic Control, Logic Gate IC
Package

SOT-23-6
Description

OR-AND Gate 1Element 3IN CMOS 6Pin SOT-23 T/R
Documentation

Datasheet

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SN74LVC1G3208DBVR Specifications

Attribute	Attribute Value

Part Number	SN74LVC1G3208DBVR
Manufacturer	TI
ChipWorker Part#	CW8111392
Category	Logic Control, Logic Gate IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	6 Pin
Case/Package	SOT-23-6
Supply Voltage (DC)	1.65V ~ 5.50V
Number of Outputs	1 Output
Output Current	32 mA
Number of Circuits	1 Circuit
Number of Positions	6 Position
Number of Bits	1 Bit
Propagation Delay Max (tpd)	3.40 ns
Voltage Nodes	5.00 V, 3.30 V, 2.50 V, 1.80 V
Number of Gates	1 Gate
Number of Inputs	3 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	1.65V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	1.65 V
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Size-Length	3.05 mm
Size-Width	1.75 mm
Size-Height	1.3 mm
Operating Temperature	-40℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Cut Tape (CT)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

DESCRIPTION
This device is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G3208 device is a single 3-input positive OR-AND gate. It performs the Boolean function Y = (A + B) ● C in positive logic. By tying one input to GND or VCC, the SN74LVC1G3208 device offers two more functions.
When C is tied to VCC, this device performs as a 2-input OR gate (Y = A + B). When A is tied to GND, the device works as a 2-input AND gate (Y = B ● C).
This B is tied device to GND also (Y works = A ●asC). a 2-input AND gate when NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
FEATURES
• Available in the Texas Instruments NanoStar™ and NanoFree™ Packages
• Supports 5-V VCC Operation
• Inputs Accept Voltages to 5.5 V
• Provides Down Translation to VCC
• Max tpd of 5 ns at 3.3 V
• Low Power Consumption, 10-µA Max ICC
• ±24-mA Output Drive at 3.3 V
• Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at the Input (Vhys = 250 mV Typ @ 3.3 V)
• Can Be Used in Three Combinations:
– OR-AND Gate
– OR Gate
– AND Gate
• Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)

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