SN74LVC1G373DCKR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LVC1G373DCKR
Manufacturer

TI
ChipWorker Part#

CW2674211
Category

Latche IC
Package

SC-70-6
Description

D-TYPE LATCH, SMD, SC-70-6, 3.3V
Documentation

Datasheet

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SN74LVC1G373DCKR Specifications

Attribute	Attribute Value

Part Number	SN74LVC1G373DCKR
Manufacturer	TI
ChipWorker Part#	CW2674211
Category	Latche IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	6 Pin
Case/Package	SC-70-6
Supply Voltage (DC)	1.65V (min)
Number of Outputs	1 Output
Output Current	32 mA
Number of Circuits	1 Circuit
Number of Positions	6 Position
Number of Bits	1 Bit
Propagation Delay Max (tpd)	3.50 ns
Number of Gates	1 Gate
Number of Inputs	1 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	1.65V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	1.65 V
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Size-Length	2.15 mm
Size-Width	1.4 mm
Size-Height	1 mm
Operating Temperature	-40℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN74LVC1G373DCKR is a single D Latch designed for 1.65 to 5.5V VCC operation. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers and working registers. While the LE input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. While the LE input is high, the Q output follows the data (D) input. When LE is taken low, the Q output is latched at the logic level set up at the D input. OE\ does not affect the internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. A buffered OE\ input can be used to place the output in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the output neither loads nor drives the bus lines significantly.
Provides down translation to VCC
Maximum tpd of 4ns at 3.3V
Ioff Supports live insertion, partial-power-down mode and back drive protection
Latch-up performance exceeds 100mA per JESD, 78 class II
10µA Maximum low power consumption
±24mA Output drive at 3.3V
Green product and no Sb/Br

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