SN74LVC1G79DCKR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LVC1G79DCKR
Manufacturer

TI
ChipWorker Part#

CW25297714
Category

Flip Flop IC
Package

SC-70-5
Description

TEXAS INSTRUMENTS SN74LVC1G79DCKR Flip-Flop, Non Inverted, Positive Edge, D, 3.8ns, 160MHz, 32mA, SC-70, 5Pins
Documentation

Datasheet

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SN74LVC1G79DCKR Specifications

Attribute	Attribute Value

Part Number	SN74LVC1G79DCKR
Manufacturer	TI
ChipWorker Part#	CW25297714
Category	Flip Flop IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	5 Pin
Case/Package	SC-70-5
Frequency	160 MHz
Supply Voltage (DC)	5.00 V, 5.50 V (max)
Number of Outputs	1 Output
Output Current	32 mA
Number of Circuits	1 Circuit
Number of Channels	1 Channel
Number of Positions	5 Position
Clock Speed	160 MHz
Number of Bits	1 Bit
Propagation Delay Max (tpd)	3.80 ns
Polarity	Non-Inverting
Number of Gates	1 Gate
Input Capacitance	4 pF
Output Current Drive	24.0 mA
Number of Inputs	1 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	1.65V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	1.65 V
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Size-Length	2 mm
Size-Width	1.25 mm
Size-Height	0.9 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
HK STC License	NLR

Product Description

The SN74LVC1G79DCKR is a single positive-edge-triggered D-type Flip-flop is designed for 1.65 to 5.5V VCC operation. When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the level at the output. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Supports down translation to VCC
Ioff Supports live insertion, partial-power-down mode and back-drive protection
Latch-up performance exceeds 100mA per JESD 78, class II
±24mA Output drive at 3.3V
Green product and no Sb/Br

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