SN74LVC2G125DCTR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LVC2G125DCTR
Manufacturer

TI
ChipWorker Part#

CW848890
Category

Logic Controller, Logic IC
Package

SSOP-8
Description

Buffer/Line Driver 2CH Non-Inverting 3-ST CMOS 8Pin SSOP T/R
Documentation

Datasheet

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SN74LVC2G125DCTR Specifications

Attribute	Attribute Value

Part Number	SN74LVC2G125DCTR
Manufacturer	TI
ChipWorker Part#	CW848890
Category	Logic Controller, Logic IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	8 Pin
Case/Package	SSOP-8
Supply Voltage (DC)	5.00 V, 5.50 V (max)
Number of Outputs	2 Output
Output Current	32.0 mA
Supply Current	250 mA
Number of Circuits	2 Circuit
Number of Channels	2 Channel
Number of Positions	8 Position
Number of Bits	2 Bit
Propagation Delay Max (tpd)	3.70 ns
Number of Gates	2 Gate
Number of Inputs	2 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	1.65V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	1.65 V
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Size-Length	3.15 mm
Size-Width	2.9 mm
Size-Height	1.2 mm
Operating Temperature	-40℃ ~ 125℃ (TA)
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
Mil-Spec	Yes
ECCN Code	EAR99

Product Description

The SN74LVC2G125DCTR is a dual Bus Buffer Gate with 3-state outputs. The dual bus buffer gate designed for 1.65 to 5.5V VCC operation. The outputs are disabled when the associated output-enable (OE) input is high. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. It is suitable for cable modem termination systems, power line communication modems, video broadcasting and infrastructure.
Supports 5V VCC operation
Latch-up performance exceeds 100mA per JESD 78, class II
ESD protection exceeds JESD 22
Maximum tpd of 4.3ns at 3.3V
Ioff Supports live insertion, partial-power-down mode and back-drive protection
10µA Maximum low power consumption ICC
±24mA Output drive at 3.3V
±50mA Continuous output current
±100mA Continuous current through VCC or GND
150°C Junction temperature
Device has limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

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