SN74LVC2G132DCTR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LVC2G132DCTR
Manufacturer

TI
ChipWorker Part#

CW38582134
Category

Logic Control, Logic Gate IC
Package

SSOP-8
Description

NAND Gate 2Element 2IN CMOS 8Pin SSOP T/R
Documentation

Datasheet

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SN74LVC2G132DCTR Specifications

Attribute	Attribute Value

Part Number	SN74LVC2G132DCTR
Manufacturer	TI
ChipWorker Part#	CW38582134
Category	Logic Control, Logic Gate IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	8 Pin
Case/Package	SSOP-8
Supply Voltage (DC)	5.00 V
Number of Outputs	1 Output
Output Current	32 A
Number of Circuits	2 Circuit
Number of Positions	8 Position
Number of Bits	2 Bit
Propagation Delay Max (tpd)	4.40 ns
Number of Gates	2 Gate
Number of Inputs	2 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	1.65V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	1.65 V
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Operating Temperature	-40℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN74LVC2G132DCTR is a dual 2-input NAND Gate with Schmitt-trigger inputs. The device performs the Boolean function Y = (A • B)\ or Y = A\ + B\ in positive logic. The device functions as two independent inverters, but because of Schmitt action, it has different input threshold levels for positive-going (VT+) and negative-going (VT-) signals. This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
±24mA Output drive at 3.3V
<0.8V at VCC = 3.3V (typical) VOLP (Output ground bounce)
>2V at VCC = 3.3V Typical VOHV (Output VOH undershoot)
10µA Maximum ICC low power consumption
Inputs accept voltages to 5.5V
Maximum tpd of 5.3ns at 3.3V
Ioff supports live insertion, partial power down mode and back drive protection
ESD protection exceeds JESD 22
Latch-up performance exceeds 100mA per JESD 78, Class II

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