SN74LVC2G14DCKR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LVC2G14DCKR
Manufacturer

TI
ChipWorker Part#

CW49783
Category

Logic Control, Logic Gate IC
Package

SC-70-6
Description

TEXAS INSTRUMENTS SN74LVC2G14DCKR Inverter Gate, LVC Family, Schmitt Trigger, 1Input, 32mA, 1.65V to 5.5V, SC-70-6
Documentation

Datasheet

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SN74LVC2G14DCKR Specifications

Attribute	Attribute Value

Part Number	SN74LVC2G14DCKR
Manufacturer	TI
ChipWorker Part#	CW49783
Category	Logic Control, Logic Gate IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	6 Pin
Case/Package	SC-70-6
Supply Voltage (DC)	5.00 V
Output Current	32 mA
Number of Circuits	2 Circuit
Number of Positions	6 Position
Number of Bits	2 Bit
Propagation Delay Max (tpd)	4.30 ns
Number of Gates	2 Gate
Number of Inputs	1 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	1.65V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	1.65 V
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Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2014/12/17

Product Description

The SN74LVC2G14DCKR is a Dual Schmitt-trigger Inverter, designed for 1.65 to 5.5V VCC operation. The SN74LVC2G14DCKR device contains two inverters and performs the Boolean function Y = A. The device functions as two independent inverters, but because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT-) signals. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
TA = 25°C Typical VOLP (output ground bounce)
>2V at VCC = 3.3V, TA = 25°C Typical VOHV (output VOH undershoot)
Ioff supports live insertion, partial power-down mode operation and back-drive protection
Supports translation down (5 to 3.3 and 3.3 to 1.8V)
Latch-up performance exceeds 100mA per JESD 78, class II
Green product and no Sb/Br
Device has limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

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