SN74LVC2G240DCTR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LVC2G240DCTR
Manufacturer

TI
ChipWorker Part#

CW14522750
Category

Logic Control, Logic Gate IC
Package

SSOP-8
Description

Buffer/Line Driver 2CH Inverting 3-ST CMOS 8Pin SSOP T/R
Documentation

Datasheet

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SN74LVC2G240DCTR Specifications

Attribute	Attribute Value

Part Number	SN74LVC2G240DCTR
Manufacturer	TI
ChipWorker Part#	CW14522750
Category	Logic Control, Logic Gate IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	8 Pin
Case/Package	SSOP-8
Supply Voltage (DC)	5.00 V, 5.50 V (max)
Number of Outputs	2 Output
Number of Circuits	2 Circuit
Number of Channels	2 Channel
Number of Positions	8 Position
Number of Bits	2 Bit
Propagation Delay Max (tpd)	4.00 ns
Number of Gates	2 Gate
Number of Inputs	1 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	1.65V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	1.65 V
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Operating Temperature	-40℃ ~ 125℃ (TA)
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN74LVC2G240DCTR is a dual Buffer Driver designed for 1.65 to 5.5V VCC operation. This device is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers and bus-oriented receivers and transmitters. This device is organized as two 1-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A input to the Y output. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor and the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using IOFF. The IOFF circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
IOFF Supports live insertion, partial-power-down mode and back-drive protection
Can be used as a down translator to translate inputs from 5.5V down to the VCC level
Latch-up performance exceeds 250mA per JESD 17
Inputs accept voltages to 5.5V
4.6ns at 3.3V Propagation delay (tpd)
10µA ICC Low power consumption
±24mA Output drive at 3.3 V
<0.8V at VCC = 3.3V, TA = 25°C VOLP (output ground bounce)
>2V at VCC = 3.3V, TA = 25°C VOHV (output VOH undershoot)
Green product and no Sb/Br

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