SN74LVC2G241DCUT - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LVC2G241DCUT
Manufacturer

TI
ChipWorker Part#

CW12923414
Category

Logic Controller, Logic IC
Package

VSSOP-8
Description

Buffer/Line Driver 2CH Non-Inverting 3-ST CMOS 8Pin VSSOP T/R
Documentation

Datasheet

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SN74LVC2G241DCUT Specifications

Attribute	Attribute Value

Part Number	SN74LVC2G241DCUT
Manufacturer	TI
ChipWorker Part#	CW12923414
Category	Logic Controller, Logic IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	8 Pin
Case/Package	VSSOP-8
Supply Voltage (DC)	-500 mV to 6.50 V
Number of Outputs	2 Output
Number of Channels	2 Channel
Number of Positions	8 Position
Number of Bits	2 Bit
Propagation Delay Max (tpd)	3.70 ns
Number of Gates	2 Gate
Number of Inputs	2 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	1.65V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	1.65 V
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Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Cut Tape (CT)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN74LVC2G241DCUT is a dual Buffer/Line Driver designed for 1.65 to 5.5V VCC operation. This device is designed specifically to improve both the performance and density of 3-state memory-address drivers, clock drivers and bus-oriented receivers and transmitters. This device is organized as two 1-bit line drivers with separate output-enable (1OE, 2OE) inputs. When 1OE is low and 2OE is high, the device passes data from the A inputs to the Y outputs. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor and OE should be tied to GND through a pull-down resistor and the minimum value of the resistor is determined by the current-sinking or the current-sourcing capability of the driver. This device is fully specified for partial-power-down applications using IOFF. The IOFF circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
IOFF Supports live insertion, partial-power-down mode and back-drive protection
Can be used as a down translator to translate inputs from 5.5V down to the VCC level
Latch-up performance exceeds 250mA per JESD 17
Inputs accept voltages to 5.5V
4.1ns at 3.3V Propagation delay (tpd)
10µA ICC Low power consumption
±24mA Output drive at 3.3 V
<0.8V at VCC = 3.3V, TA = 25°C VOLP (output ground bounce)
>2V at VCC = 3.3V, TA = 25°C VOHV (output VOH undershoot)
Green product and no Sb/Br

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