SN74LVC2G74DCUR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LVC2G74DCUR
Manufacturer

TI
ChipWorker Part#

CW348444
Category

Flip Flop IC
Package

VSSOP-8
Description

Flip-Flop, Differential / Complementary, Positive Edge, 74LVC74, D, 4.1ns, 200MHz, 32mA, VSSOP
Documentation

Datasheet

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SN74LVC2G74DCUR Specifications

Attribute	Attribute Value

Part Number	SN74LVC2G74DCUR
Manufacturer	TI
ChipWorker Part#	CW348444
Category	Flip Flop IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	8 Pin
Case/Package	VSSOP-8
Frequency	200 MHz
Supply Voltage (DC)	5.00 V, 5.50 V (max)
Number of Outputs	1 Output
Output Current	32 mA
Number of Circuits	1 Circuit
Number of Positions	8 Position
Clock Speed	200 MHz
Number of Bits	1 Bit
Propagation Delay Max (tpd)	4.40 ns
Polarity	Non-Inverting, Inverting
Number of Gates	2 Gate
Input Capacitance	5 pF
Number of Inputs	1 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	1.65V ~ 5.5V
Supply Voltage (Max)	6.5 V
Supply Voltage (Min)	1.65 V
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Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2014/12/17

Product Description

The SN74LVC2G74DCUR is a single Positive-edge-triggered D-type Flip-flop with clear and preset. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D-input can be changed without affecting the levels at the outputs.
5.9ns at 3.3V Maximum TPD
Low power consumption
IOFF supports live insertion, partial-power-down mode and back-drive protection
Latch-up performance exceeds 100mA per JESD 78
ESD protection exceeds JESD 22
This device has limited built-in ESD protection, leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

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