SN74LVC541ADW - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LVC541ADW
Manufacturer

TI
ChipWorker Part#

CW14574382
Category

Logic Controller, Logic IC
Package

SOIC-20
Description

Buffer/Line Driver 8CH Non-Inverting 3-ST CMOS 20Pin SOIC Tube
Documentation

Datasheet

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SN74LVC541ADW Specifications

Attribute	Attribute Value

Part Number	SN74LVC541ADW
Manufacturer	TI
ChipWorker Part#	CW14574382
Category	Logic Controller, Logic IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	20 Pin
Case/Package	SOIC-20
Supply Voltage (DC)	2.00V ~ 3.60V
Number of Outputs	8 Output
Number of Circuits	8 Circuit
Number of Channels	8 Channel
Number of Positions	20 Position
Number of Bits	8 Bit
Propagation Delay Max (tpd)	5.10 ns
Voltage Nodes	3.30 V, 2.70 V, 2.50 V, 1.80 V
Output Current Drive	-1.00 mA
Number of Inputs	8 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	1.65V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	1.65 V
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Size-Length	12.8 mm
Size-Width	7.52 mm
Size-Height	2.35 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2014/12/17
ECCN Code	EAR99

Product Description

The SN74LVC541ADW is an octal Buffer/Driver with 3-state outputs and designed for 1.65 to 3.6V VCC operation. The device features inputs and outputs facilitate printed circuit board layout. The 3-state control gate is a 2-input AND gate with active-low inputs so that, if either output enable (OE1 or OE2) input is high, all eight outputs are in the high-impedance state. Inputs can be driven from either 3.3/5V devices. This feature allows the use of these devices as translators in a mixed 3.3/5V system environment. This device is fully specified for partial-power-down applications using IOFF. The IOFF circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor and the minimum value of the resistor is determined by the current-sinking capability of the driver.
Support mixed-mode signal operation on all ports
IOFF Supports partial-power-down mode operation
Latch-up performance exceeds 250mA per JESD 17
Inputs accept voltages to 5.5V
5.1ns at 3.3V Propagation delay (tpd)
<0.8V at VCC = 3.3V, TA = 25°C VOLP (output ground bounce)
>2V at VCC = 3.3V, TA = 25°C VOHV (output VOH undershoot)
Green product and no Sb/Br

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