SN74LVC574APW - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LVC574APW
Manufacturer

TI
ChipWorker Part#

CW15430303
Category

Flip Flop IC
Package

TSSOP-20
Description

TEXAS INSTRUMENTS SN74LVC574APW Flip-Flop, Tri State Non Inverted, Positive Edge, 74LVC574, D, 4.6ns, 150MHz, 24mA, TSSOP
Documentation

Datasheet

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SN74LVC574APW Specifications

Attribute	Attribute Value

Part Number	SN74LVC574APW
Manufacturer	TI
ChipWorker Part#	CW15430303
Category	Flip Flop IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	20 Pin
Case/Package	TSSOP-20
Frequency	150 MHz
Supply Voltage (DC)	2.00V ~ 3.60V
Number of Outputs	8 Output
Output Current	24 mA
Number of Circuits	8 Circuit
Number of Positions	20 Position
Clock Speed	150 MHz
Number of Bits	8 Bit
Propagation Delay Max (tpd)	8.50 ns
Voltage Nodes	3.30 V, 2.70 V, 2.50 V, 1.80 V
Input Capacitance	4 pF
Output Current Drive	-1.00 mA
Number of Inputs	8 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	1.65V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	1.65 V
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Operating Temperature	-40℃ ~ 125℃ (TA)
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN74LVC574APW is an octal edge-triggered D-type Flip-flop with 3-state outputs. It is designed for 1.65 to 3.6V VCC operation. It is designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers and working registers. On the positive transition of the clock input, the Q outputs are set to the logic levels at the data (D) inputs. A buffered OE\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pull-up components. OE\ does not affect the internal operations of the flip-flops.
7ns at 3.3V Maximum tpd
Support mixed-mode signal operation on all ports
Ioff Supports partial-power-down mode operation
Latch-up performance exceeds 250mA per JESD 17
Green product and no Sb/Br

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