SN74LVC74APWR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LVC74APWR
Manufacturer

TI
ChipWorker Part#

CW4346134
Category

Flip Flop IC
Package

TSSOP-14
Description

TEXAS INSTRUMENTS SN74LVC74APWR Flip-Flop, Complementary, Positive Edge, 74LVC74, D, 5.2ns, 100MHz, 50mA, TSSOP
Documentation

Datasheet

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SN74LVC74APWR Specifications

Attribute	Attribute Value

Part Number	SN74LVC74APWR
Manufacturer	TI
ChipWorker Part#	CW4346134
Category	Flip Flop IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	14 Pin
Case/Package	TSSOP-14
Frequency	100 MHz
Supply Voltage (DC)	2.00V ~ 3.60V
Number of Outputs	1 Output
Output Current	50 mA
Number of Circuits	2 Circuit
Number of Positions	14 Position
Clock Speed	150 MHz
Number of Bits	2 Bit
Propagation Delay Max (tpd)	5.20 ns
Polarity	Non-Inverting, Inverting
Voltage Nodes	3.30 V, 2.70 V, 2.50 V, 1.80 V
Input Capacitance	5 pF
Output Current Drive	-1.00 mA
Number of Inputs	1 Input
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	1.65V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	1.65 V
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Size-Length	5 mm
Size-Width	4.4 mm
Size-Height	1.15 mm
Operating Temperature	-40℃ ~ 125℃ (TA)
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99
HK STC License	NLR

Product Description

The SN74LVC74APWR is a dual positive-edge-triggered D-type Flip-flop designed for 1.65 to 3.6V VCC operation. A low level at the preset (PRE\\) or clear (CLR\\) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. The data I/Os and control inputs are overvoltage tolerant. This feature allows the use of these devices for down-translation in a mixed-voltage environment.
Maximum tpd of 5.2ns at 3.3V
Latch-up performance exceeds 250mA per JESD 17
Green product and no Sb/Br

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