SN74LVCE161284DLR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LVCE161284DLR
Manufacturer

TI
ChipWorker Part#

CW8562678
Category

Logic Control, Logic Gate IC
Package

SSOP-48
Description

Translation Transceiver 0°C to 70℃ 48Pin SSOP T/R
Documentation

Datasheet

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SN74LVCE161284DLR Specifications

Attribute	Attribute Value

Part Number	SN74LVCE161284DLR
Manufacturer	TI
ChipWorker Part#	CW8562678
Category	Logic Control, Logic Gate IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	48 Pin
Case/Package	SSOP-48
Supply Voltage (DC)	3.00V ~ 3.60V
Output Current	84.0 mA
Number of Bits	19 Bit
Voltage Nodes	3.30 V
Operating Temperature (Max)	70 ℃
Operating Temperature (Min)	0 ℃
Supply Voltage	3V ~ 3.6V
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Operating Temperature	0℃ ~ 70℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free

Product Description

The SN74LVCE161284 is designed for 3-V to 3.6-V VCC operation. This device provides asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.
This device has eight bidirectional bits; data can flow in the A-to-B direction when the direction-control input (DIR) is high and in the B-to-A direction when DIR is low. This device also has five drivers that drive the cable side, and four receivers. The SN74LVCE161284 has one receiver dedicated to the HOST LOGIC line and a driver to drive the PERI LOGIC line.
The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in a totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive requirements as specified in the IEEE Std 1284-I (level-1 type) and IEEE Std 1284-II (level-2 type) parallel peripheral-interface specifications. Except for HOST LOGIC IN and peripheral logic out (PERI LOGIC OUT), all cable-side pins have a 1.4-k integrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low state or if the output voltage is above VCC CABLE. If VCC CABLE is off, PERI LOGIC OUT is set to low.
The device has two supply voltages. VCC is designed for 3-V to 3.6-V operation. VCC CABLE supplies the inputs and output buffers of the cable side only and is designed for 3-V to 3.6-V and for 4.7-V to 5.5-V operation. Even when VCC CABLE is 3 V to 3.6 V, the cable-side I/O pins are 5-V tolerant.
The Y outputs (Y9Y13) stay in the high state after power on until an associated input (A9A13) goes high. When an associated input goes high, all Y outputs are activated, and noninverting signals of the associated inputs are driven through Y outputs. This special feature prevents printer-system errors caused by deasserting the BUSY signal in the cable at power on.

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