SN74LVCH16245ADGGR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LVCH16245ADGGR
Manufacturer

TI
ChipWorker Part#

CW9055868
Category

Logic Controller, Logic IC
Package

TSSOP-48
Description

16Bit Bus Transceiver With 3-State Outputs 48-TSSOP -40℃ to 125℃
Documentation

Datasheet

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SN74LVCH16245ADGGR Specifications

Attribute	Attribute Value

Part Number	SN74LVCH16245ADGGR
Manufacturer	TI
ChipWorker Part#	CW9055868
Category	Logic Controller, Logic IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	48 Pin
Case/Package	TSSOP-48
Supply Voltage (DC)	2.00V ~ 3.60V
Number of Outputs	16 Output
Number of Circuits	2 Circuit
Number of Channels	16 Channel
Number of Positions	48 Position
Number of Bits	16 Bit
Propagation Delay Max (tpd)	5.80 ns
Voltage Nodes	3.30 V, 2.70 V, 2.50 V, 1.80 V
Output Current Drive	-1.00 mA
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	1.65V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	1.65 V
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Size-Length	12.6 mm
Size-Width	6.2 mm
Size-Height	1.05 mm
Operating Temperature	-40℃ ~ 125℃ (TA)
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
ECCN Code	EAR99
HK STC License	NLR

Product Description

The SN74LVCH16245ADGGR is a 16-bit non-inverting Bus Transceiver with 3-state outputs and designed for 1.65 to 3.6V VCC operation. This device is designed for asynchronous communication between data buses. This device can be used as two 8-bit transceivers or one 16-bit transceiver. Active bus-hold circuitry holds unused or un-driven data inputs at a valid logic state. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. Active bus-hold circuitry holds unused or un-driven data inputs at a valid logic state. Use of pull-up/pull-down resistors with the bus-hold circuitry is not recommended. The bus-hold circuitry is part of the input circuit and is not disabled by OE or DIR.
Supports mixed-mode signal operation on all ports
IOFF Supports live insertion, partial-power-down mode and back-drive protection
Bus hold on data inputs eliminates the need for external pull-up/pull-down resistors
Latch-up performance exceeds 250mA per JESD 17
4ns at 3.3V Propagation delay (tpd)
<0.8V at VCC = 3.3V, TA = 25°C VOLP (output ground bounce)
>2V at VCC = 3.3V, TA = 25°C VOHV (output VOH undershoot)
Green product and no Sb/Br

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