SN74LVCH16T245DGGR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LVCH16T245DGGR
Manufacturer

TI
ChipWorker Part#

CW5938424
Category

Voltage Level Translator IC
Package

TSSOP-48
Description

Bus Transceiver, LVC Family, 16Input, 32mA, 6ns, 1.65V to 5.5V, TSSOP-48
Documentation

Datasheet

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SN74LVCH16T245DGGR Specifications

Attribute	Attribute Value

Part Number	SN74LVCH16T245DGGR
Manufacturer	TI
ChipWorker Part#	CW5938424
Category	Voltage Level Translator IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	48 Pin
Case/Package	TSSOP-48
Supply Voltage (DC)	1.65V ~ 5.50V
Number of Outputs	16 Output
Output Current	32 mA
Number of Circuits	2 Circuit
Number of Channels	16 Channel
Number of Positions	48 Position
Number of Bits	16 Bit
Propagation Delay Max (tpd)	6.00 ns
Voltage Nodes	1.80 V, 2.50 V, 3.30 V, 5.00 V
Output Current Drive	-1.00 mA
Number of Inputs	16 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Number of Output Channels	8 Channel
Supply Voltage	1.65V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	1.65 V
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Size-Length	12.6 mm
Size-Width	6.2 mm
Size-Height	1.05 mm
Operating Temperature	-40℃ ~ 85℃ (TA)
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN74LVCH16T245DGGR is a 16-bit dual-supply Bus Transceiver configurable voltage translation and 3-state outputs. The SN74LVCH16T245 device is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A-bus to the B-bus when the B-port outputs are activated and from the B-bus to the A-bus when the A-port outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.
Control inputs VIH/VIL levels are referenced to VCCA voltage
Overvoltage-tolerant inputs and outputs allow mixed-voltage-mode data communications
Bus hold on data inputs eliminates the need for external pull up and pull down resistors
IOFF supports partial-power-down mode operation
Latch-up performance exceeds 100mA per JESD 78
ESD protection exceeds JESD 22
This device has limited built-in ESD protection, leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

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